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16-bit, +/-0.65 lsb inl, 500 ksps pulsar ? differential adc in msop/qfn preliminary technical data ad7693 rev. prb information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features application diagram 16-bit resolution with no missing codes ad7693 ref gnd vdd in+ in? vio sdi sck sdo cnv +1.8v to vdd 3- or 4-wire interface (spi, daisy chain, cs) +2.5v to +5v 10v, 5v, ... +5v ada4941-1 -001 throughput: 500 ksps inl: +/-0.25 lsb typical, 0.6 5 lsb max (10 ppm of fsr) dynamic range: 96.5 db typical @ 500 ksps sinad: 96 db typical @ 1 khz, ref = 5v thd: ?120 db typical @ 1 khz. ref = 5v true differential analog input range: vref 0 v to v ref with v ref up to v dd on both inputs no pipeline delay figure 2. single-supply 5 v operation with table 1. msop, qfn 1 (lfcsp)/sot-23 14-/16-/18-bit pulsar adc 1.8 v/2.5 v/3 v/5 v logic interface serial interface spi?/qspi?/microwire?/dsp-compatible 400 ksps to 500 ksps daisy-chain multiple adcs and busy indicator 100 ksps 250 ksps adc driver power dissipation type 4 mw @ 5 v/100 ksps 18-bit ad7691 AD7690 ada4941-1 40 w @ 5 v/1 ksps ada4841-x standby current: 1 na ad7684 ad7687 ad7688 10-lead package: msop (msop-8 size) and 3 mm 3 mm qfn 1 (lfcsp) (sot-23 size) pin-for-pin compatible with the ad7687 , ad7688 and 18-bit AD7690 and ad7691 applications battery-powered equipment data acquisitions seismic data acquisition systems dvms instrumentation medical instruments figure 1. integral nonlinearity vs. code 16-bit true differential ad7693 ada4941-1 ada4841-x 16-bit pseudo ad7683 ad7685 ad7686 ada4841-x ad7680 ad7694 differential/ unipolar 14-bit ad7940 ad7942 ad7946 ada4841-x 1 qfn package in developm ent. contact sales for samples and availability. general description the ad7693 is a 16-bit, successive approximation, analog-to- digital converter (adc) that operates from a single power supply, vdd. it contains a low power, high speed, 16-bit sampling adc with no missing codes, an internal conversion clock, and a versatile serial interface port. on the cnv rising edge, it samples the voltage difference between the in+ and in? pins. the voltages on these pins swing in opposite phase between 0 v and ref. the reference voltage, ref, is applied externally and can be set up to the supply voltage, vdd. its power scales linearly with throughput. the spi-compatible serial interface also features the ability, using the sdi input, to daisy-chain several adcs on a single, 3-wire bus and provides an optional busy indicator. it is compatible with 1.8 v, 2.5 v, 3 v, or 5 v logic, using the separate vio supply. the ad7693 is housed in a 10-lead msop or a 10-lead qfn 1 (lfcsp) with operation specified from ?40c to +85c. 1 qfn package in developm ent. contact sales for samples and availability.
ad7693 preliminary technical data rev. prb | page 2 of 24 table of contents features .............................................................................................. 1 applications....................................................................................... 1 application diagram........................................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing specifications....................................................................... 5 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 pin configurations and function descriptions ........................... 7 terminology ...................................................................................... 8 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 12 circuit information.................................................................... 12 converter operation.................................................................. 12 typical connecti on diagram ................................................... 13 analog inputs.............................................................................. 14 driver amplifier choice ........................................................... 14 single-to-differential driver .................................................... 15 voltage reference input ............................................................ 15 power supply............................................................................... 15 supplying the adc from the reference.................................. 16 digital interface.......................................................................... 16 cs mode 3-wire, no busy indicator..................................... 17 cs mode 3-wire with busy indicator ................................... 18 cs mode 4-wire, no busy indicator..................................... 19 cs mode 4-wire with busy indicator ................................... 20 chain mode, no busy indicator ........................................... 21 chain mode with busy indicator........................................... 22 application hints ........................................................................... 23 layout .......................................................................................... 23 evaluating the ad7693s performance.................................... 23 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history
preliminary technical data ad7693 rev. prb | page 3 of 24 specifications vdd = 4.5 v to 5.5 v, vio = 2.3 v to vdd, v ref = vdd, all specifications t min to t max , unless otherwise noted. table 2. parameter conditions/comments min typ max unit resolution 18 bits analog input voltage range in+ ? (in?) ?v ref +v ref v absolute input voltage in+, in? ?0.1 v ref + 0.1 v common-mode input range in+, in? 0 v ref /2 v ref /2 + 0.1 v analog input cmrr f in = 250 khz 65 db leakage current at 25c acquisition phase 1 na input impedance 1 throughput conversion rate 0 500 ksps transient response full-scale step 400 ns accuracy no missing codes 16 bits integral linearity error ?0.65 0.25 +0.65 lsb differential linearity error ?0.5 0.2 +0.5 lsb 2 transition noise ref = vdd = 5 v 0.16 lsb gain error 3 -30 1.5 +30 lsb gain error temperature drift 0.5 ppm/c zero error 3 ?10 +10 lsb zero temperature drift 1 ppm/c power supply sensitivity vdd = 5 v 5% 1 ppm ac accuracy dynamic range v ref = 5 v 96 96.5 db 4 signal-to-noise f in = 1 khz, v ref = 5 v 95.5 96 db f in = 1 khz, v ref = 2.5 v 93 db spurious-free dynamic range f in = 1 khz, v ref = 5 v ?120 db total harmonic distortion f in = 1 khz, v ref = 5 v ?120 db signal-to-(noise + distortion) f in = 1 khz, v ref = 5 v 95.5 96 db intermodulation distortion 5 tbd db 1 see the analog inputs section. 2 lsb means least significant bit. with the 5 v input range, one lsb is 152.6 v. 3 see the terminology section. these specif ications include full temperature range variation but not the error contribution from the external reference. 4 all specifications in db are referred to a full-scale input fsr. tested with an input signal at 0.5 db below full scale, unles s otherwise specified. 5 f in1 = 21.4 khz and f in2 = 18.9 khz, with each tone at ?7 db below full scale.
ad7693 preliminary technical data rev. prb | page 4 of 24 vdd = 4.5 v to 5.5 v, vio = 2.3 v to vdd, v ref = vdd, all specifications t min to t max , unless otherwise noted. table 3. parameter conditions/comments min typ max unit reference voltage range 0.5 vdd + 0.3 v load current 500 ksps, ref = 5 v 100 a sampling dynamics ?3 db input bandwidth 9 mhz aperture delay vdd = 5v 2.5 ns digital inputs logic levels v il ?0.3 +0.3 vio v v ih 0.7 vio vio + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format serial 16 bits twos complement pipeline delay 1 v ol i sink = +500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies vdd specified performance 4. 5 5.5 v vio specified performance 2.3 vdd + 0.3 v vio range 1.8 vdd + 0.3 v standby current 2 , 3 vdd and vio = 5 v, 25c 1 50 na power dissipation 100 sps throughput 5 w 100 ksps throughput 5 mw 500 ksps throughput 15 mw energy per conversion 50 nj/sample temperature range 4 specified performance t min to t max ?40 +85 c 1 conversion results available immediately after completed conversion. 2 with all digital inputs forced to vio or gnd as required. 3 during acquisition phase. 4 contact an analog devices sales representative for extended temperature range.
preliminary technical data ad7693 rev. prb | page 5 of 24 timing specifications vdd = 4.5 v to 5.5 v, vio = 2.3 v to vdd, v ref = vdd, all specifications t min to t max , unless otherwise noted. table 4. 1 parameter symbol min typ max unit conversion time: cnv rising edge to data available t conv 0.5 1.6 s acquisition time t acq 400 ns time between conversions t cyc 2.0 s cnv pulse width ( cs mode) t cnvh 10 ns sck period ( cs mode) t sck 15 ns sck period (chain mode) t sck vio above 4.5 v 17 ns vio above 3 v 18 ns vio above 2.7 v 19 ns vio above 2.3 v 20 ns sck low time t sckl 7 ns sck high time t sckh 7 ns sck falling edge to data remains valid t hsdo 4 ns sck falling edge to data valid delay t dsdo vio above 4.5 v 14 ns vio above 3 v 15 ns vio above 2.7 v 16 ns vio above 2.3 v 17 ns cnv or sdi low to sdo d15 msb valid ( cs mode) t en vio above 4.5 v 15 ns vio above 2.7 v 18 ns vio above 2.3 v 22 ns cnv or sdi high or last sck falling edge to sdo high impedance ( cs mode) t dis 25 ns sdi valid setup time from cnv rising edge ( cs mode) t ssdicnv 15 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 0 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns sck valid hold time from cnv rising edge (chain mode) t hsckcnv 10 ns sdi valid setup time from sck falling edge (chain mode) t ssdisck 3 ns sdi valid hold time from sck falling edge (chain mode) t hsdisck 4 ns sdi high to sdo high (chain mode with busy indicator) t dsdosdi vio above 4.5 v 15 ns vio above 2.3 v 26 ns 1 see figure 3 and figure 4 for load conditions.
ad7693 preliminary technical data rev. prb | page 6 of 24 absolute maximum ratings table 5. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter rating analog inputs in+, in? gnd ? 0.3 v to vdd + 0.3 v or 130 ma 1 1 ref gnd ? 0.3 v to vdd + 0.3 v supply voltages vdd, vio to gnd ?0.3 v to +7 v vdd to vio 7 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance (msop-10) 200c/w jc thermal impedance (msop-10) 44c/w lead temperature range jedec j-std-20 1 see the analog inputs section. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. 500a i ol 500a i oh 1.4v t o sdo c l 50pf -002 figure 3. load circuit fo r digital interface timing 30% vio 70% vio 2v or vio ? 0.5v 1 0.8v or 0.5v 2 0.8v or 0.5v 2 2v or vio ? 0.5v 1 t delay t delay 1 2v if vio above 2.5v, vio ? 0.5v if vio below 2.5v. 2 0.8v if vio above 2.5v, 0.5v if vio below 2.5v. -003 figure 4. voltage levels for timing
preliminary technical data ad7693 rev. prb | page 7 of 24 pin configurations and function descriptions 1ref 2vdd 3in+ 4 in? 5gnd 10 vio notes 1. qfn package in development. contact sales for samples and availability. 9 sdi 8 sck 7 sdo 6 cnv top view (not to scale) ad7693 -005 ref 1 vdd 2 in+ 3 in? 4 gnd 5 vio 10 sdi 9 sck 8 sdo 7 cnv 6 ad7693 top view (not to scale) -004 figure 5. 10-lead msop pin configuration figure 6. 10-lead qfn (lfcsp) pin configuration table 6. pin function descriptions pin no. mnemonic type description 1 1 ref ai reference input voltage. the ref range is from 0.5 v to vdd. it is referred to the gnd pin. this pin should be decoupled closely to the pin with a 10 f capacitor. 2 vdd p power supply. 3 in+ ai differential positive analog input. 4 in? ai differential negative analog input. 5 gnd p power supply ground. 6 cnv di convert input. this input has multiple functions. on its leading edge, it initiates the conversions and selects the interface mode of the part; chain or cs mode. in chain mode, the data should be read when cnv is high. in cs mode, it enables the sdo pin when low. 7 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 8 sck di serial data clock input. when the part is selected, the conversion result is shifted out by this clock. 9 sdi di serial data input. this input provides multiple features. it selects the interface mode of the adc as follows: chain mode is selected if sdi is low during the cnv rising edge. in this mode, sdi is used as a data input to daisy-chain the conversion results of two or more adcs onto a single sdo line. the digital data level on sdi is output on sdo with a delay of 16 sck cycles. cs mode is selected if sdi is high during the cn v rising edge. in this mode, either sdi or cnv can enable the serial output signals when low, an d if sdi or cnv is low when the conversion is complete, the busy indicator feature is enabled. 10 vio p input/output interface digital power. nominally at the same supply as the host interface (1.8 v, 2.5 v, 3 v, or 5 v). 1 ai = analog input, di = digital input, do = digital output, and p = power.
ad7693 preliminary technical data rev. prb | page 8 of 24 terminology least significant bit (lsb) the least significant bit, or lsb, is the smallest increment that can be represented by a converter. for an analog-to-digital con- verter with n bits of resolution, the lsb expressed in volts is effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad by the following formula: enob = ( sinad db ? 1.76)/6.02 n inp-p v vlsb 2 )( = and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in db. integral nonlinearity error (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line (see dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. the value for dynamic range is expressed in decibels. figure 25 ). signal-to-noise ratio (snr) differential nonlinearity error (dnl) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. zero error signal-to-(noise + distortion) ratio (sinad) zero error is the difference between the ideal midscale voltage, that is, 0 v, from the actual voltage producing the midscale output code, that is, 0 lsb. sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. gain error the first transition (from 100 . . . 00 to 100 . . . 01) should occur at a level ? lsb above nominal negative full scale (?4.999847 v for the 5 v range). the last transition (from 011 10 to 011 11) should occur for an analog voltage 1? lsb below the nominal full scale (+4.999771 v for the 5 v range.) the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. aperture delay aperture delay is the measure of the acquisition performance. it is the time between the rising edge of the cnv input and when the input signal is held for a conversion. transient resp onse transient response is the time required for the adc to accurately acquire its input after a full-scale step function is applied. spurious-free dynamic range (sfdr) sfdr is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal.
preliminary technical data ad7693 rev. prb | page 9 of 24 typical performance characteristics figure 7. integral nonlinearity vs. code figure 10. differential nonlinearity vs. code figure 11. histogram of a dc input at the code transition figure 8. histogram of a dc input at the code center figure 9. fft plot figure 12. snr vs. input level
ad7693 preliminary technical data rev. prb | page 10 of 24 figure 13. snr, sinad, and enob vs. reference voltage figure 16. thd, sfdr vs. reference voltage figure 14. snr vs. temperature figure 17. thd vs. temperature figure 15. sinad vs. frequency figure 18. thd vs. frequency
preliminary technical data ad7693 rev. prb | page 11 of 24 1000 0 supply (v) vdd operating current (a) 05792-041 4.50 5.50 750 500 250 f s = 100ksps vdd vio 4.75 5.00 5.25 figure 22. offset and gain error vs. temperature figure 19. operating currents vs. supply sdo capacitive load (pf) 120 0 20406080100 t dsdo delay (ns) 25 20 15 10 5 0 vdd = 5v, 85c vdd = 5v, 25c 0 5792-034 temperature ( c) power-down current (na) 1000 750 500 250 0 ?55 ?35 ?15 5 25 45 65 85 105 125 vdd + vio 0 5792-033 figure 20. power-down currents vs. temperature figure 23. t dsdo delay vs. capacitance load and supply 1000 ?6 supply (v) operating current (a) 05792-042 ?55 125 750 500 250 f s = 100ksps vdd vio ?35?155 25456585105 figure 21. operating currents vs. temperature
ad7693 preliminary technical data rev. prb | page 12 of 24 theory of operation sw+ msb 16,384c in+ lsb comp control logic switches control busy output code cnv ref gnd in? 4c 2c c c 32,768c sw? msb 16,384c lsb 4c 2c c c 32,768c -024 figure 24. adc simplified schematic circuit information the ad7693 is a fast, low power, single-supply, precise, 16-bit adc using a successive approximation architecture. the ad7693 is capable of converting 500,000 samples per second (500 ksps) and powers down between conversions. when operating at 1 ksps, for example, it consumes 40 w typically, ideal for battery-powered applications. the ad7693 provides the user with an on-chip track-and-hold and does not exhibit pipeline delay or latency, making it ideal for multiple multiplexed channel applications. the ad7693 is specified from 4.5 v to 5.5 v and can be interfaced to any 1.8 v to 5 v digital logic family. it is housed in a 10-lead msop or a tiny 10-le ad qfn (lfcsp) that combines space savings and allows flexible configurations. it is pin-for-pin compatible with the 16-bit ad7687 and ad7688 and with the 18-bit AD7690 and ad7691 . converter operation the ad7693 is a successive approximation adc based on a charge redistribution dac. figure 24 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 16 binary-weighted capacitors, which are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the comparators input are connected to gnd via sw+ and sw?. all independent switches are connected to the analog inputs. thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? inputs. when the acquisition phase is complete and the cnv input goes high, a conversion phase is initiated. when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. therefore, the differential voltage between the inputs in+ and in? captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and ref, the comparator input varies by binary-weighted voltage steps (v ref /2, v ref /4 ... v ref /32,768). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the part returns to the acquisition phase, and the control logic generates the adc output code and a busy signal indicator. because the ad7693 has an on-board conversion clock, the serial clock, sck, is not required for the conversion process.
preliminary technical data ad7693 rev. prb | page 13 of 24 typical connection diagram transfer functions figure 26 shows an example of the recommended connection diagram for the ad7693 when multiple supplies are available. the ideal transfer characteristic for the ad7693 is shown in figure 25 and table 7 . 100...000 100...001 100...010 011...101 011...110 011...111 adc code (twos complement) analog input +fsr ? 1.5lsb +fsr ? 1lsb ?fsr + 1lsb ?fsr ?fsr + 0.5lsb -025 figure 25. adc ideal transfer function table 7. output codes and ideal input voltages analog input v ref = 5 v digital output code (hex) description fsr ? 1 lsb +4.999847 v 0x7fff 1 midscale + 1 lsb +152.6 v 0x0001 midscale 0 v 0x0000 midscale ? 1 lsb ?152.6 v 0xffff ?fsr + 1 lsb ?4.999847 v 0x8001 ?fsr ?5 v 0x8000 2 1 this is also the code for an overranged analog input (v in+ ? v in? above v ref ? v gnd ). 2 this is also the code for an underranged analog input (v in+ ? v in? below v gnd ). ad7693 ref gnd vdd in? in+ vio sdi sck sdo cnv 3- or 4-wire interface 5 100nf 100nf 5v 10f 2 v+ v+ v? 1.8v to vdd ref 1 0 to v ref 2.7nf 4 v+ v? v ref to 0 2.7nf ada4841-2 3 ada4841-2 3 4 1 see reference section for reference selection. 2 c ref is usually a 10f ceramic capacitor (x5r). 3 see table 8 for additional recommended amplifiers. 4 optional filter. see analog input section. 5 see the digital interface section for most convenient interface mode. -026 15 15 figure 26. typical application diagram with multiple supplies
ad7693 preliminary technical data rev. prb | page 14 of 24 when the source impedance of the driving circuit is low, the ad7693 can be driven directly. large source impedances significantly affect the ac performance, especially total harmonic distortion (thd). the dc performances are less sensitive to the input impedance. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency. analog inputs figure 27 shows an equivalent circuit of the input structure of the ad7693. the two diodes, d1 and d2, provide esd protection for the analog inputs, in+ and in?. care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 0.3 v because this causes the diodes to become forward biased and start conducting current. these diodes can handle a forward-biased current of 130 ma maximum. for instance, these conditions could eventually occur when the input buffers (u1) supplies are different from vdd. in such a case, for example, an input buffer with a short-circuit, the current limitation can be used to protect the part. driver amplifier choice although the ad7693 is easy to drive, the driver amplifier must meet the following requirements: ? the noise generated by the driver amplifier needs to be kept as low as possible to preserve the snr and transition noise performance of the ad7693. the noise coming from the driver is filtered by the ad7693 analog input circuits 1-pole, low-pass filter made by rin and cin or by the external filter, if one is used. because the typical noise of the ad7693 is 56 v rms, the snr degradation due to the amplifier is c in r in d1 d2 c pin in+ or in? gnd v dd -027 ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + = ? ? n n loss nefnef snr figure 27. equivalent analog input circuit the analog input structure allows the sampling of the true differential signal between in+ and in?. by using these differential inputs, signals common to both inputs are rejected. where: f ?3 db is the input bandwidth in megahertz of the ad7693 (9 mhz) or the cutoff frequency of the input filter, if one is used. n is the noise gain of the amplifier (for example, 1 in buffer configuration). e n is the equivalent input noise voltage of the op amp, in nv/hz. 90 40 1 10000 frequency (khz) cmrr (db) -028 10 100 1000 85 80 75 70 65 60 55 50 45 v ref = vdd = 5v ? for ac applications, the driver should have a thd performance commensurate with the ad7693. ? for multichannel multiplexed applications, the driver amplifier and the ad7693 analog input circuit must settle for a full-scale step onto the capacitor array at an 16-bit level (0.0015%, 15 ppm). in the amplifiers data sheet, settling at 0.1% to 0.01% is more commonly specified. this could differ significantly from the settling time at an 16-bit level and should be verified prior to driver selection. figure 28. analog input cmrr vs. frequency during the acquisition phase, the impedance of the analog inputs (in+ and in?) can be modeled as a parallel combination of the capacitor, c pin , and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 600 and is a lumped component made up of serial resistors and the on resistance of the switches. c in is typically 30 pf and is mainly the adc sampling capacitor. table 8. recommended driver amplifiers amplifier typical application ada4941-1 very low noise, low power single to differential ada4841-x very low noise, small, and low power ad8655 5 v single supply, low noise ad8021 very low noise and high frequency during the conversion phase, where the switches are opened, the input impedance is limited to c pin . r in and c in make a 1- pole, low-pass filter that reduces undesirable aliasing effects and limits the noise. ad8022 low noise and high frequency op184 low power, low noise, and low frequency ad8605 , ad8615 5 v single supply, low power
preliminary technical data ad7693 rev. prb | page 15 of 24 if desired, smaller reference decoupling capacitor values down to 2.2 f can be used with a minimal impact on performance, especially dnl. single-to-differ ential driver for applications using a single-ended analog signal, either bipolar or unipolar, the ada4941-1 single-ended-to-differential driver allows for a differential input into the part. the schematic is shown in regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) between the ref and gnd pins. figure 29 . r1 and r2 set the attenuation ratio between the input range and the adc range (v ref ). r1, r2, and c f will be chosen depending on the desired input resistance, signal bandwidth, antialiasing and noise contribution. for example, for the 10 v range with a 4 k impedance, r2 = 1 k and r1 = 4 k. power supply the ad7693 uses two power supply pins: a core supply, vdd, and a digital input/output interface supply, vio. vio allows direct interface with any logic between 1.8 v and v dd . to reduce the supplies needed, the vio and vdd pins can be tied together. the ad7693 is independent of power supply sequencing between vio and vdd. additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in r3 and r4 set the common mode on the in? input, and r5 and r6 set the common mode on the in+ input of the adc. the common mode should be set close to v ref /2; however, if single supply is desired, it can be set slightly above v ref /2 to provide some headroom for the figure 30 . ada4941-1 output stage. for example, for the 10 v range with a single supply, r3 = 8.45 k, r4 = 11.8 k, r5 = 10.5 k, and r6 = 9.76 k. 90 40 1 10000 frequency (khz) cmrr (db) -030 10 100 1000 85 80 75 70 65 60 55 50 45 v ref = vdd = 5v ad7693 ref gnd vdd in+ 2.7nf 100nf 2.7nf in? +5v ref 10v, 5v, ... +5.2v +5.2v 15 10f r2 c f ada4941 r1 r3 100nf r5 r4 r6 -029 15 figure 30. psrr vs. frequency the ad7693 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate. this makes the part ideal for low sampling rate (even a few hertz) and low battery-powered applications. figure 29. single-ended-to- differential driver circuit voltage reference input the ad7693 voltage reference input, ref, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the ref and gnd pins, as explained in the 1000 10 0.1 0.001 10 1m sampling rate (sps) operating current (a) -031 100 1k 100k 10k vdd = 5v vio 10000 100 1 0.01 layout section. when ref is driven by a very low impedance source, for example, a reference buffer using the ad8031 or the ad8605 , a 10 f (x5r, 0805 size) ceramic chip capacitor is appropriate for optimum performance. if an unbuffered reference voltage is used, the decoupling value depends on the reference used. for instance, a 22 f (x5r, 1206 size) ceramic chip capacitor is appropriate for optimum performance using low temperature drift adr43x and adr44x references. figure 31. operating currents vs. sample rate
ad7693 preliminary technical data rev. prb | page 16 of 24 supplying the adc from the reference adsp-219x. in this mode, the ad7693 can use either a 3-wire or 4-wire interface. a 3-wire interface using the cnv, sck, and sdo signals minimizes wiring connections useful, for instance, in isolated applications. a 4-wire interface using the sdi, cnv, sck, and sdo signals allows cnv, which initiates the conversions, to be independent of the readback timing (sdi). this is useful in low jitter sampling or simultaneous sampling applications. for simplified applications, the ad7693, with its low operating current, can be supplied directly using the reference circuit shown in figure 32 . the reference line can be driven by ? the system power supply directly. ? a reference voltage with enough current output capability, such as the adr43x . when in chain mode, the ad7693 provides a daisy-chain feature using the sdi input for cascading multiple adcs on a single data line similar to a shift register. ? a reference buffer, such as the ad8031 , which can also filter the system power supply, as shown in figure 32 . ad8031 ad7693 vio ref vdd 10f 1f 10 10k 5v 5v 5v 1f 1 -032 1 optional reference buffer and filter. the mode in which the part operates depends on the sdi level when the cnv rising edge occurs. the cs mode is selected if sdi is high, and the chain mode is selected if sdi is low. the sdi hold time is such that when sdi and cnv are connected together, the chain mode is selected. in either mode, the ad7693 offers the option of forcing a start bit in front of the data bits. this start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. otherwise, without a busy indicator, the user must timeout the maximum conversion time prior to readback. figure 32. example of application circuit digital interface the busy indicator feature is enabled though the ad7693 has a reduced number of pins, it offers flexibility in its serial interface modes. ? in the cs mode if cnv or sdi is low when the adc conversion ends (see figure 36 and figure 40 ). cs when in mode, the ad7693 is compatible with spi, qspi, digital hosts, and dsps, for example, blackfin? adsp-bf53x or ? in the chain mode if sck is high during the cnv rising edge (see figure 44 ).
preliminary technical data ad7693 rev. prb | page 17 of 24 cs mode 3-wire, no busy indicator this mode is usually used when a single ad7693 is connected to an spi-compatible digital host. the connection diagram is shown in figure 33 , and the corresponding timing is given in figure 34 . with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. once a conversion is initiated, it continues until completion irrespective of the state of cnv. this could be useful, for instance, to bring cnv low to select other spi devices, such as analog multiplexers; however, cnv must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad7693 enters the acquisition phase and powers down. when cnv goes low, the msb is output onto sdo. the remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge will allow a faster reading rate, provided it has an acceptable hold time. after the 16 th sck falling edge, or when cnv goes high, whichever is earlier, sdo returns to high impedance. cnv sck sdo sdi data in clk convert v io digital host ad7693 -033 cs figure 33. 3-wire mode without busy indicator connection diagram (sdi high) sdo d15 d14 d13 d1 d0 t dis sck 123 141516 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition sdi = 1 t cnvh t acq t en 034 cs figure 34. 3-wire mode without busy indicator seri al interface timing (sdi high)
ad7693 preliminary technical data rev. prb | page 18 of 24 cs mode 3-wire with busy indicator this mode is usually used when a single ad7693 is connected to an spi-compatible digital host having an interrupt input. the connection diagram is shown in figure 35 , and the corresponding timing is given in figure 36 . with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. sdo is maintained in high impedance until the completion of the conversion irrespective of the state of cnv. prior to the minimum conversion time, cnv can be used to select other spi devices, such as analog multiplexers, but cnv must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impedance. with a pull-up on the sdo line, this transition can be used as an interrupt signal to initiate the data reading controlled by th e digital host. the ad7693 then enters the acquisition phase and powers down. the data bits are clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge will allow a faster reading rate, provided it has an acceptable hold time. after the optional 17 th sck falling edge, or when cnv goes high, whichever is earlier, sdo returns to high impedance. if multiple ad7693s are selected at the same time, the sdo output pin handles this contention without damage or induced latch-up. meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. data in irq clk convert vio digital host cnv sck sdo sdi v io ad7693 -035 cs figure 35. 3-wire mode with busy indicator connection diagram (sdi high) sdo d15 d14 d1 d0 t dis sck 1 2 3 15 16 17 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition sdi = 1 t cnvh t acq -036 cs figure 36. 3-wire mode with busy indi cator serial interface timing (sdi high)
preliminary technical data ad7693 rev. prb | page 19 of 24 cs mode 4-wire, no busy indicator this mode is usually used when multiple ad7693s are connected to an spi-compatible digital host. a connection diagram example using two ad7693s is shown in figure 37 , and the corresponding timing is given in figure 38 . with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback. (if sdi and cnv are low, sdo is driven low.) prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multiplexers, but sdi must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad7693 enters the acquisition phase and powers down. each adc result can be read by bringing its sdi input low, which consequently outputs the msb onto sdo. the remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge will allow a faster reading rate, provided it has an acceptable hold time. after the 16 th sck falling edge, or when sdi goes high, whichever is earlier, sdo returns to high impedance and another ad7693 can be read. data in clk cs1 convert cs2 digital host cnv sck sdo sdi cnv sck sdo sdi ad7693 ad7693 -037 cs figure 37. 4-wire mode without busy indicator connection diagram sdo d15 d14 d13 d1 d0 t dis sck 123 303132 t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi(cs1) cnv t ssdicnv t hsdicnv d1 14 15 t sck t sckl t sckh d0 d16 d15 17 18 16 sdi(cs2) -038 cs figure 38. 4-wire mode without busy indicato r serial interface timing
ad7693 preliminary technical data rev. prb | page 20 of 24 cs mode 4-wire with busy indicator this mode is usually used when a single ad7693 is connected to an spi-compatible digital host, which has an interrupt input, and it is desired to keep cnv, which is used to sample the analog input, independent of the signal used to select the data reading. this requirement is particularly important in applications where low jitter on cnv is desired. the connection diagram is shown in figure 39 , and the corresponding timing is given in figure 40 . with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback. (if sdi and cnv are low, sdo is driven low.) prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multiplexers, but sdi must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impedance. with a pull-up on the sdo line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. the ad7693 then enters the acquisition phase and powers down. the data bits are clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge will allow a faster reading rate, provided it has an acceptable hold time. after the optional 17 th sck falling edge, or sdi going high, whichever is earlier, sdo returns to high impedance. data in irq clk convert cs1 vio digital host cnv sck sdo sdi ad7693 -039 cs figure 39. 4-wire mode with busy indicator connection diagram sdo d15 d14 d1 d0 t dis sck 1 2 3 151617 t sck t sckl t sckh t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi cnv t ssdicnv t hsdicnv -040 cs figure 40. 4-wire mode with busy indicator serial interface timing
preliminary technical data ad7693 rev. prb | page 21 of 24 chain mode, no busy indicator this mode can be used to daisy-chain multiple ad7693s on a 3-wire serial interface. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using two ad7693s is shown in figure 41 , and the corresponding timing is given in figure 42 . when sdi and cnv are low, sdo is driven low. with sck low, a rising edge on cnv initiates a conversion, selects the chain mode, and disables the busy indicator. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when the conversion is complete, the msb is output onto sdo and the ad7693 enters the acquisition phase and powers down. the remaining data bits stored in the internal shift register are clocked by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 16 n clocks are required to read back the n adcs. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge will allow a faster reading rate and consequently more ad7693s in the chain, provided the digital host has an acceptable hold time. the maximum conversion rate can be reduced due to the total readback time. clk convert data in digital host cnv sck sdo sdi cnv sck sdo sdi ad7693 b ad7693 a -041 figure 41. chain mode without busy indicator connection diagram sdo a = sdi b d a 15 d a 14 d a 13 sck 1 2 3 30 31 32 t ssdisck t hsdisc t en conversion acquisition t conv t cyc t acq acquisition cnv d a 1 14 15 t sck t sckl t sckh d a 0 17 18 16 sdi a = 0 sdo b d b 15 d b 14 d b 13 d a 1 d b 1d b 0d a 15 d a 14 t hsdo t dsdo t ssckcnv t hsckcnv d a 0 -042 figure 42. chain mode without busy indicator serial interface timing
ad7693 preliminary technical data rev. prb | page 22 of 24 chain mode with busy indicator this mode can also be used to daisy chain multiple ad7693s on a 3-wire serial interface while providing a busy indicator. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using three ad7693s is shown in figure 43 , and the corresponding timing is given in figure 44 . when sdi and cnv are low, sdo is driven low. with sck high, a rising edge on cnv initiates a conversion, selects the chain mode, and enables the busy indicator feature. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when all adcs in the chain have completed their conversions, the sdo pin of the adc closest to the digital host (see the ad7693 adc labeled c in figure 43 ) is driven high. this transition on sdo can be used as a busy indicator to trigger the data readback controlled by the digital host. the ad7693 then enters the acquisition phase and powers down. the data bits stored in the internal shift register are clocked out, msb first, by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 16 n + 1 clocks are required to readback the n adcs. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and consequently more ad7693s in the chain, provided the digital host has an acceptable hold time. clk convert data in irq digital host cnv sck sdo sdi cnv sck sdo sdi cnv sck sdo sdi ad7693 b ad7693 c ad7693 a -043 figure 43. chain mode with bu sy indicator connection diagram sdo a = sdi b d a 15 d a 14 d a 13 sck 123 35 47 48 t en conversion acquisition t conv t cyc t acq acquisition cnv = sdi a d a 1 415 t sck t sckh t sckl d a 0 17 34 16 sdo b = sdi c d b 15 d b 14 d b 13 d a 1 d b 1d b 0d a 15 d a 14 49 t ssdisck t hsdisc t hsdo t dsdo sdo c d c 15 d c 14 d c 13 d a 1d a 0 d c 1d c 0d a 14 19 31 32 18 33 d b 1d b 0d a 15 d b 15 d b 14 t dsdosdi t ssckcnv t hsckcnv d a 0 t dsdosdi t dsdosdi t dsdosdi t dsdosdi -044 figure 44. chain mode with busy indicator serial interface timing
preliminary technical data ad7693 rev. prb | page 23 of 24 application hints -045 layout the printed circuit board that houses the ad7693 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the ad7693, with all its analog signals on the left side and all its digital signals on the right side, eases this task. avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the ad7693 is used as a shield. fast switching signals, such as cnv or clocks, should not run near analog signal paths. crossover of digital and analog signals should be avoided. at least one ground plane should be used. it could be common or split between the digital and analog sections. in the latter case, the planes should be joined underneath the ad7693s. figure 45. example layout of the ad7693 (top layer) -046 the ad7693 voltage reference input ref has a dynamic input impedance and should be decoupled with minimal parasitic inductances. this is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the ref and gnd pins and connecting them with wide, low impedance traces. finally, the power supplies vdd and vio of the ad7693 should be decoupled with ceramic capacitors, typically 100 nf, placed close to the ad7693 and connected using short and wide traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. an example of a layout following these rules is shown in figure 45 and figure 46 . evaluating the ad7693s performance figure 46. example layout of the ad7693 (bottom layer) other recommended layouts for the ad7693 are outlined in the documentation of the evaluation board for the ad7693 ( eval-ad7693 -cb ). the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval-control brd3 .
ad7693 preliminary technical data rev. prb | page 24 of 24 outline dimensions compliant to jedec standards mo-187-ba 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.05 0.33 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc pin 1 coplanarity 0.10 3.10 3.00 2.90 3.10 3.00 2.90 5.15 4.90 4.65 figure 47.10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters 3.00 bsc sq index are a top view 1.50 bcs sq exposed pad (bot tom view) 1.74 1.64 1.49 2.48 2.38 2.23 1 6 10 0.50 bsc 0.50 0.40 0.30 5 pin 1 indicator 0.80 0.75 0.70 0.05 max 0.02 nom seating plane 0.30 0.23 0.18 0.20 ref 0.80 max 0.55 typ side view paddle connected to gnd. this connection is not required to meet the electrical performances qfn package in development. contact sales for samples and availability. figure 48. 10-lead lead frame chip scale package [qfn (lfcsp_wd)] 3 mm 3 mm body, very very thin, dual lead (cp-10-9) dimensions shown in millimeters ordering guide model temperature range ordering quantity pa ckage description package option branding eval-ad7693cb evaluation board 1 eval-control brd2 controller board 2 eval-control brd3 controller board 2 1 this board can be used as a standalone evaluation board or in conjunction with the eval-control brdx for evaluation/demonstrat ion purposes. 2 these boards allow a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. pr05793-9/06(prb)

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